Layout Engineer
Date: Mar 18, 2023
Location: Lexington, MA, US
Company: MIT Lincoln Laboratory
Group 89—Quantum Information and Integrated Nanosystems Group
The Quantum Information and Integrated Nanosystems Group conducts quantum information science research from a shared foundation of innovative control-signal design, outstanding fabrication tools, and well-equipped measurement laboratories. The group has a broad range of experimental and prototyping activities. The group's quantum information science activities include the development of superconducting and trapped-ion qubits and quantum sensing with nitrogen-vacancy (NV) centers in diamond. In addition, the group has robust capabilities in classical superconducting circuits, complementary metal-oxide semiconductor (CMOS) design and fabrication, and integrated photonics. These component technologies are used in synergy with quantum information science demonstrations, as well as in standalone applications that include beyond-CMOS circuit technologies, energy-starved sensors, compact optical communication and laser radar transceivers, and microwave photonic signal processing.
Job Description
The group is seeking an experienced layout and mask design engineer to work on layouts for integrated photonics, quantum computing, and other emerging integrated circuit technologies. These technologies will be fabricated both in-house and in foundry-available processes. The engineer will work in the Cadence environment, with which they should be fluent, and will have responsibility for the full layout project from basic layout cell creation to final tapeout. Key tasks will include coding layout pcells; writing technology files; and laying out devices, test structures, systems, and full mask reticles based on input from device and process designers. They will also be responsible for working with the layout team to update and maintain a device pcell library, and for implementing revision control standards and documenting layout changes. They will help in the implementation of DRC and LVS decks, and final masks are expected to be DRC and LVS clean, when DRC and LVS decks are available. Assignments will be somewhat complex in nature and judgement will be required in resolving moderately complex problems.
Requirements:
Minimum:
- Expertise (>2 years) with coding layout pcells in the Cadence Virtuoso (SKILL) environment
- Experience using verification runsets, Experience developing verification runsets (ideally with Calibre SVRF or Cadence PVS) preferred
- Experience developing or supporting Process Design Kits (PDKs)
- Strong communication and team-based collaboration skills
- Ability to problem solve independently
Also Desired:
- Experience developing technology files and design environments in Cadence
- Experience with the Advanced Node version of Cadence
- Cadence CurvyCore experience
- Experience coding with Perl, TCL, or Python
- Integrated photonic or RF layout design experience
For Benefits Information, click http://hrweb.mit.edu/benefits
Selected candidate will be subject to a pre-employment background investigation and must be able to obtain and maintain a Secret level DoD security clearance.
To safeguard our health and well-being, MIT Lincoln Laboratory requires COVID-19 vaccination for all employees. Individuals may request exemption from the vaccine requirement for medical or religious reason.
MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required.
Requisition ID: 39441
Nearest Major Market: Boston
Job Segment:
Manufacturing Engineer, Security Clearance, Design Engineer, Laboratory, DoD, Engineering, Government, Science
